armviz

CSSELR_EL1

64-bitIdentification

Which cache to ask about next. Write a level and a type, then read CLIDR_EL1 or the cache's own ID register. It is a selector rather than a register in its own right, and it only has an effect on the next CLSR.

Field layout

—
3:1
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0

Current value hover a field to locate it

B7
B6
B5
B4
B3
B2
B1
B0

Fields

BitsFieldBitsValueDescription
63:4—60Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
3:1Level[3:1]30x0

Which cache level to select.

0Type[0:0]10x0

0 to select a data cache, 1 to select an instruction cache.