armviz

FPCR

64-bitFloating point

Floating-point control register: the knobs that change how arithmetic behaves rather than recording what happened. Rounding mode, denormal handling and exception trap enables all live here, and they apply to both scalar and Advanced SIMD instructions.

Fields that depend on optional floating-point features are listed only where defined in the base architecture.

Field layout

—
26
25
24
23:22
21:20
19
18:16
15
12
11
10
9
8
—
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0

Current value hover a field to locate it

B7
B6
B5
B4
B3
B2
B1
B0

Fields

BitsFieldBitsValueDescription
63:27—37Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
26AHP[26]1

Alternative half-precision. Selects the alternative half-precision conversion format instead of IEEE half-precision. The FEAT_FP16 instructions ignore this bit.

0
IEEE half-precision
1
Alternative half-precision
25DN[25]1

Default NaN. When set, any operation with a NaN operand returns the default NaN rather than propagating the incoming NaN.

0
Propagate input NaN
1
Return the default NaN
24FZ[24]1

Flush-to-zero. When set, denormalized inputs and outputs of single- and double-precision instructions become zero. This is the classic performance-versus-precision trade.

0
Denormals pass through
1
Denormals flushed to zero
23:22RMode[23:22]2

Rounding mode used by every floating-point result, scalar and vector alike.

0
Round to nearest
1
Round towards plus infinity
2
Round towards minus infinity
3
Round towards zero
21:20Stride[21:20]2

No function in AArch64 state. Retained only so the AArch32 FPSCR can be saved and restored faithfully.

0
Unused in AArch64
19FZ16[19]1

Flush-to-zero for half-precision. The 16-bit counterpart of FZ.

0
Half denormals pass through
1
Half denormals flushed to zero
18:16Len[18:16]3

No function in AArch64 state. Retained only for AArch32 FPSCR context saving.

0
Unused in AArch64
15IDE[15]1

Trap on input denormal. When set, a denormal input raises the exception instead of quietly setting the FPSR cumulative bit.

0
Untrapped, FPSR.IDC is set
1
Trapped
14:13—2Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
12IXE[12]1

Trap on inexact. Stops the common case where a result cannot be represented exactly from raising anything at all.

0
Untrapped, FPSR.IXC is set
1
Trapped
11UFE[11]1

Trap on underflow.

0
Untrapped, FPSR.UFC is set
1
Trapped
10OFE[10]1

Trap on overflow.

0
Untrapped, FPSR.OFC is set
1
Trapped
9DZE[9]1

Trap on divide by zero.

0
Untrapped, FPSR.DZC is set
1
Trapped
8IOE[8]1

Trap on invalid operation, for example an invalid NaN operand combination.

0
Untrapped, FPSR.IOC is set
1
Trapped
7:0—8Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
← CurrentELFPSR →