PMCR_EL0
64-bitDebugThe performance monitor's master control: whether counting is on, how many counters exist, and whether they can be programmed from EL0. Read N and P to find out what the chip actually offers, rather than assuming the architectural minimum.
Field layout
—
14:12
LC[11:8]11:8
7:5
2
1
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
Current value hover a field to locate it
B7
B6
B5
B4
B3
B2
B1
B0
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 63:15 | — | 49 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 14:12 | XO[14:12] | 3 | 0x0 | Extended counter capability. |
| 11:8 | LC[11:8] | 4 | 0x0 | Long event counter capability. |
| 7:5 | N[7:5] | 3 | 0x0 | How many counters exist. Read this rather than assuming five. |
| 4:3 | — | 2 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 2 | C[2:2] | 1 | 0x0 | Cycle counter increment. Clear it to count instructions instead of cycles. |
| 1 | P[1:1] | 1 | 0x0 | User-mode access permitted. |
| 0 | E[0:0] | 1 | 0x0 | Enable. Counting does not start until this is set. |