SCTLR_EL2
64-bitMemory managementWhether the MMU and caches are on at EL2, and how this level handles exceptions. A hypervisor turns this on as the last step of setting up a guest.
Field layout
—
RES1[31:27]31:27
26
25:24
23
—
12
—
4
3
2
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
Current value hover a field to locate it
B7
B6
B5
B4
B3
B2
B1
B0
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 63:32 | — | 32 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 31:27 | RES1[31:27] | 5 | 0x0 (0) | Reserved. |
| 26 | UAO[26:26] | 1 | 0x0 | Imprecise abort flag for EL1. |
| 25:24 | RES0[25:24] | 2 | 0x0 | Reserved. |
| 23 | SPAN[23:23] | 1 | 0x0 | PAN flag for EL1. |
| 22:13 | — | 10 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 12 | I[12] | 1 | 0x0 | Instruction cache enable. |
| 11:5 | — | 7 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 4 | SA0[4] | 1 | 0x0 | Stack alignment check for EL0. |
| 3 | SA[3] | 1 | 0x0 | Stack alignment check for EL1. |
| 2 | C[2] | 1 | 0x0 | Data cache enable. |
| 1 | — | 1 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 0 | M[0] | 1 | 0x0 | MMU enable. Setting it takes effect only after an ISB, and getting that wrong is a common cause of 'the MMU is on but the old mappings are still being used'. |