SPSR_EL3
64-bitTrapThe processor state to restore when returning from an exception at EL3.
Field layout
63:62
61
60
I[59:56]59:56
—
47
43
42
—
PSTATE[31:0]31:0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
Current value hover a field to locate it
B7
B6
B5
B4
B3
B2
B1
B0
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 63:62 | M[63:62] | 2 | 0x0 | Mode to return to. |
| 61 | D[61] | 1 | 0x0 | Process state was AArch32. |
| 60 | A[60] | 1 | 0x0 | Instruction state was AArch32. |
| 59:56 | I[59:56] | 4 | 0x0 | Which of the four exception masks were active. |
| 55:48 | — | 8 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 47 | N[47] | 1 | 0x0 | Condition flags were valid on entry. |
| 46:44 | — | 3 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 43 | C[43] | 1 | 0x0 | Carry clear. |
| 42 | V[42] | 1 | 0x0 | Overflow clear. |
| 41:32 | — | 10 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 31:0 | PSTATE[31:0] | 32 | 0x0 (0) | The PSTATE fields this register mirrors, including the interrupt mask bits in the top nibble. |