CPACR_EL1

32-bitFloating point

Controls whether floating-point, Advanced SIMD and vector instructions are permitted to execute, and which levels may use them. EL1 software normally clears the FPEN field to its reset value and thus has the hardware trap every floating-point instruction to itself.

Many further fields here are tied to optional features such as SME and pointer authentication, and are implementation-defined. Only the base architectural fields are listed.

Field layout

—

21:20

17:16

—

byte 3

byte 2

byte 1

byte 0

Current value hover a field to locate it

Fields

Bits	Field	Bits	Description
31:29	—	3	Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
28	TTA[28]	1	Trap trace register access, routing accesses to trace registers from EL0 and EL1 to EL1. 0 Trace register access from lower levels trapped 1 Access not trapped
27:22	—	6	Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
21:20	FPEN[21:20]	2	Floating-point and Advanced SIMD enable. The value 11 is the only one that allows the instructions to run. 0 Trap all floating-point and SIMD instructions 1 Reserved 2 Reserved 3 Allow floating-point and SIMD instructions
19:18	—	2	Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
17:16	ZEN[17:16]	2	SVE enable, when the vector extension is implemented. 0 Trap SVE instructions 2 Reserved 3 Allow SVE instructions
15:0	—	16	Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.

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