SCTLR_EL1
32-bitMemory managementside-effectingThe system control register for EL1: one flag per subsystem, deciding whether the MMU runs, whether caches are on, which unprivileged system registers EL0 may touch, and how strict EL1 wants its own memory accesses to be. The register whose change has the largest immediate effect on subsequent instruction execution.
This register has grown with every revision of the architecture and now carries many fields tied to optional features. Only the core architectural fields are shown; the gaps between them are genuinely reserved or feature-dependent.
Field layout
Current value hover a field to locate it
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 31:27 | — | 5 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 26 | UCI[26] | 1 | Trap access to the EL0 system registers from EL1 and EL2. On by default, which is why user code needs an explicit service call to read its own thread pointer.
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| 25 | EE[25] | 1 | Endianness for EL1 data accesses.
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| 24 | E0E[24] | 1 | Endianness for EL0 data accesses. The bit numbering runs the opposite way from the architecture's byte order, so this is 0 for little-endian.
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| 23 | SPAN[23] | 1 | Prohibit certain speculative accesses. When set, speculative loads cannot cross a page boundary, closing a class of side-channel leak.
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| 22:20 | — | 3 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 19 | WXN[19] | 1 | Write execute never. Makes any page mapped as both writable and executable raise a permission fault instead. The default on any serious system.
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| 18:13 | — | 6 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 12 | I[12] | 1 | Instruction cache enable for EL1 and below.
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| 11:5 | — | 7 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 4 | SA0[4] | 1 | The same check for EL0.
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| 3 | SA[3] | 1 | Stack alignment check. When set, SP must stay 16-byte aligned at EL1, and an SP whose low bits are non-zero causes an exception on any instruction that uses it as a base.
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| 2 | C[2] | 1 | Data cache enable for EL1 and below. Independent of the instruction cache bit.
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| 1 | — | 1 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 0 | M[0] | 1 | MMU enable. Cleared at reset; an operating system turns this on once the page tables are in place, at which point every memory access starts going through a translation walk.
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