armviz

TTBR0_EL1

64-bitMemory management

Root of the page table walk for the lower half of the address space, the region TTBR1_EL1 does not cover. The low bits of the register are configuration borrowed from TCR_EL1, so the two are read together.

The size, cache and shareability fields of this register are defined by TCR_EL1 and are not repeated here. Together the two describe one translation regime.

Field layout

ASID[63:48]63:48
BASE[47:3]47:3
2:1
0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0

Current value hover a field to locate it

B7
B6
B5
B4
B3
B2
B1
B0

Fields

BitsFieldBitsValueDescription
63:48ASID[63:48]160x0 (0)

An address space identifier that tags this translation regime. Entries in the page tables are tagged to match, which is what lets several processes share one set of page tables.

47:3BASE[47:3]450x0 (0)

Base address of the root translation table. The low three bits hold configuration rather than address, so the effective alignment is 8 bytes.

2:1SKL[2:1]2

Skip level. Says how many levels of the walk are bypassed, so a 4KB granule system with 4 levels can skip one when only 2GB pages are ever used.

0
No levels skipped
1
One level skipped
2
Two levels skipped
3
Three levels skipped
0CnP[0]10x0

Common not private, when FEAT_TTCNP is implemented. Makes the walk read from a single location shared across cores.

← SCTLR_EL1TTBR1_EL1 →