TTBR1_EL1

64-bitMemory management

Root of the page table walk for the upper half of the address space, conventionally the range that kernel code lives in. Separate from TTBR0_EL1 so a process can map its own pages low down while the kernel stays high up.

As with TTBR0_EL1, the size and cache fields are defined by TCR_EL1.

Field layout

ASID[63:48]63:48

BASE[47:3]47:3

2:1

byte 7

byte 6

byte 5

byte 4

byte 3

byte 2

byte 1

byte 0

Current value hover a field to locate it

Fields

Bits	Field	Bits	Value	Description
63:48	ASID[63:48]	16	0x0 (0)	Address space identifier for this translation regime. In practice EL1 normally runs with TTBR1 untagged.
47:3	BASE[47:3]	45	0x0 (0)	Base address of the high-half root translation table, with the low three bits reserved for configuration.
2:1	SKL[2:1]	2		Skip level for the TTBR1 walk. 0 No levels skipped 1 One level skipped 2 Two levels skipped 3 Three levels skipped
0	—	1		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.

← TTBR0_EL1 TCR_EL1 →