TCR_EL1

64-bitMemory managementside-effecting

Describes the shape of the page tables that TTBR0_EL1 and TTBR1_EL1 point at: how big an address space each covers, how the walk caches memory, and whether tag checks apply. A translation regime only makes sense when this and both base registers agree.

This is a large register with many extension-dependent fields. The core architectural fields governing the low and high halves are listed here; fields above bit 38 and the optional tagging and MTE controls are omitted.

Field layout

—

34:32

31:30

29:28

27:26

25:24

T1SZ[21:16]21:16

15:14

13:12

11:10

9:8

T0SZ[5:0]5:0

byte 7

byte 6

byte 5

byte 4

byte 3

byte 2

byte 1

byte 0

Current value hover a field to locate it

Fields

Bits	Field	Bits	Value	Description
63:39	—	25		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
38	TBI1[38]	1		Tag checking for the TTBR1 walk. Must be set for addresses using the top byte as a memory tag. 0 Top byte ignored 1 Top byte checked as a tag
37	TBI0[37]	1		Tag checking for the TTBR0 walk. 0 Top byte ignored 1 Top byte checked as a tag
36:35	—	2		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
34:32	IPS[34:32]	3		Physical address size, as log2 of the number of bytes addressable. A value below the implemented physical size truncates addresses. 0 As ID_AA64MMFR0.PARange 1 36-bit 2 40-bit 3 42-bit 4 48-bit 5 52-bit 6 56-bit
31:30	TG1[31:30]	2		Granule size for the TTBR1 walk, as log2 of the bytes per granule. 0 4 KiB 1 64 KiB 2 16 KiB 3 Reserved
29:28	SH1[29:28]	2		Shareability of the TTBR1 walk. Decides which inner shareable domain page table fetches belong to. 0 Non-shareable 2 Outer shareable 3 Inner shareable
27:26	ORGN1[27:26]	2		Outer cacheability for the TTBR1 walk. 0 Non-cacheable 1 Write-back, write-allocate 2 Write-through, no write-allocate 3 Write-back, no write-allocate
25:24	IRGN1[25:24]	2		Inner cacheability for the TTBR1 walk, using the same encoding as ORGN1. 0 Non-cacheable 1 Write-back, write-allocate 2 Write-through, no write-allocate 3 Write-back, no write-allocate
23:22	—	2		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
21:16	T1SZ[21:16]	6	0x0 (0)	Log2 of the size of the TTBR1 address range. Combined with the 48-bit virtual address space this gives how many levels of walk are needed and where the split falls.
15:14	TG0[15:14]	2		Granule size for the TTBR0 walk. 0 4 KiB 1 64 KiB 2 16 KiB 3 Reserved
13:12	SH0[13:12]	2		Shareability of the TTBR0 walk. 0 Non-shareable 2 Outer shareable 3 Inner shareable
11:10	ORGN0[11:10]	2		Outer cacheability for the TTBR0 walk. 0 Non-cacheable 1 Write-back, write-allocate 2 Write-through, no write-allocate 3 Write-back, no write-allocate
9:8	IRGN0[9:8]	2		Inner cacheability for the TTBR0 walk. 0 Non-cacheable 1 Write-back, write-allocate 2 Write-through, no write-allocate 3 Write-back, no write-allocate
7:6	—	2		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
5:0	T0SZ[5:0]	6	0x0 (0)	Log2 of the size of the TTBR0 address range.

← TTBR1_EL1 MAIR_EL1 →