CTR_EL0

64-bitGeneric

Cache topology register: the parameters software needs in order to clean and invalidate caches correctly. Read from EL0, so an interrupt handler can maintain the cache without a system call.

Field layout

—

CWG[27:24]27:24

ERG[23:20]23:20

DminLine[19:16]19:16

15:14

—

IminLine[3:0]3:0

byte 7

byte 6

byte 5

byte 4

byte 3

byte 2

byte 1

byte 0

Current value hover a field to locate it

Fields

Bits	Field	Bits	Value	Description
63:30	—	34		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
29	DIC[29]	1		Data cache clean to the point of unification, needed before an instruction cache invalidate when the two are not coherent with each other. 0 Clean to the point of unification is required 1 Clean to the point of unification is not required
28	IDC[28]	1		Instruction cache invalidate requirements for data to instruction coherence. 0 A BIC that does not operate at EL0 is required 1 Not required
27:24	CWG[27:24]	4	0x0	Log2 of the cache writeback granule, in words. Defines the largest block a cache clean may write back at once.
23:20	ERG[23:20]	4	0x0	Log2 of the exclusives reservation granule, in bytes. Bounds how fine-grained an atomic instruction's reservation can be.
19:16	DminLine[19:16]	4	0x0	Log2 of the number of words in the smallest data cache line.
15:14	L1Ip[15:14]	2		Level 1 instruction cache policy, saying how it is indexed and tagged. 0 Virtually indexed, physically tagged 1 Physically indexed, physically tagged 2 Virtually indexed, virtually tagged 3 Reserved
13:4	—	10		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
3:0	IminLine[3:0]	4	0x0	Log2 of the number of words in the smallest instruction cache line.

← TPIDRRO_EL0 ID_AA64PFR0_EL1 →