ID_AA64PFR0_EL1
64-bitIdentificationThe first of the architectural feature identification registers, each nibble answering one yes-or-no question about the processor. Software reads these at startup to decide which code paths to take.
Every field uses the same enumeration: 0 means not implemented, 1 means implemented at version 1, and 1111 means look at the named feature instead. Many further fields exist for later features and are omitted.
Field layout
Current value hover a field to locate it
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 63:52 | — | 12 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 51:48 | DIT[51:48] | 4 | Data independent timing, which lets a program promise it does not leak through timing side channels.
| |
| 47:36 | — | 12 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 35:32 | SVE[35:32] | 4 | Scalable Vector Extension version, for 128-bit and larger register tiles.
| |
| 31:28 | RAS[31:28] | 4 | Reliability, availability and serviceability extension version.
| |
| 27:24 | — | 4 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 23:20 | AdvSIMD[23:20] | 4 | Advanced SIMD support, the 128-bit vector instructions.
| |
| 19:16 | FP[19:16] | 4 | Floating-point support, so whether FP instructions are available at all.
| |
| 15:12 | EL3[15:12] | 4 | AArch64 support at EL3.
| |
| 11:8 | EL2[11:8] | 4 | AArch64 support at EL2.
| |
| 7:4 | EL1[7:4] | 4 | AArch64 support at EL1.
| |
| 3:0 | EL0[3:0] | 4 | AArch64 support at EL0.
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