ID_AA64PFR1_EL1

64-bitIdentification

Which A64 floating-point features are present, beyond the first register's set: bigger vectors, more vector lengths, half-precision support. A feature-detect routine reads this to find out what it is allowed to use.

Field layout

—

byte 7

byte 6

byte 5

byte 4

byte 3

byte 2

byte 1

byte 0

Current value hover a field to locate it

Fields

Bits	Field	Bits	Value	Description
63:32	—	32		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
31	SVEBF16[31:31]	1	0x0	SVE BFloat16.
30	CSV2[30:30]	1	0x0	CSV2 extension.
29	—	1		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
28	RCPC3[28:28]	1	0x0	RCpc-based memory ordering.
27:21	—	7		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
20	DP[20:20]	1	0x0	Dot product.
19:13	—	7		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
12	FHM[12:12]	1	0x0	Fused multiply-add, half-precision.
11:9	—	3		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
8	ASIMDHP[8:8]	1	0x0	Advanced SIMD half-precision support.
7:5	—	3		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
4	FP16[4:4]	1	0x0	Full-precision half-precision support.
3:1	—	3		Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise.
0	FPHP[0:0]	1	0x0	Half-precision support.

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