ID_AA64MMFR0_EL1
64-bitIdentificationWhich memory-management features are present, and the most important field on the whole register: PARange, the physical address width. A program that writes this register's PARange field is how Linux discovers how wide the address bus is.
Field layout
—
PARange[37:32]37:32
31:29
26
25
24
ASID[23:20]23:20
19
18:17
16
UAO[15:12]15:12
IDC[11:8]11:8
IC[7:4]7:4
TFR[3:0]3:0
byte 7
byte 6
byte 5
byte 4
byte 3
byte 2
byte 1
byte 0
Current value hover a field to locate it
B7
B6
B5
B4
B3
B2
B1
B0
Fields
| Bits | Field | Bits | Value | Description |
|---|---|---|---|---|
| 63:38 | — | 26 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 37:32 | PARange[37:32] | 6 | 0x0 (0) | Physical address width: 32, 36, 40, 42, 44, 48 or 52 bits. This is what a bootloader reads to find out how much address space the chip has. |
| 31:29 | ASID16[31:29] | 3 | 0x0 | 16-bit ASID support. |
| 28:27 | — | 2 | Not assigned to a documented field. Values written here are reserved and should be treated as read-as-zero unless the architecture says otherwise. | |
| 26 | PAN[26:26] | 1 | 0x0 | Privileged access never. |
| 25 | LPA[25:25] | 1 | 0x0 | Larger page sizes. |
| 24 | LPD[24:24] | 1 | 0x0 | Late permission check. |
| 23:20 | ASID[23:20] | 4 | 0x0 | ASID for EL1. |
| 19 | TIL[19:19] | 1 | 0x0 | TLB invalidate instruction by VA. |
| 18:17 | TWL[18:17] | 2 | 0x0 | TLB invalidate by VA, all levels. |
| 16 | TIR[16:16] | 1 | 0x0 | TLB invalidate by VA, EL1. |
| 15:12 | UAO[15:12] | 4 | 0x0 | Imprecise abort at EL0 to EL2. |
| 11:8 | IDC[11:8] | 4 | 0x0 | Data cache maintenance by VA to PoC. |
| 7:4 | IC[7:4] | 4 | 0x0 | Instruction cache maintenance by VA to PoU. |
| 3:0 | TFR[3:0] | 4 | 0x0 | Translation table format. |